The Economist walks through the basics of integrated circuit design and construction, digging into the factors that limit future miniaturization and speed increases.

As a relative newbie when it comes to chip design, I found the whole article to be very readable. One central point:

Unfortunately, as transistors get smaller, more defects creep in. There is thus a trade-off between complexity and cost. And, while the cost per transistor is almost inversely proportional to the number of transistors crammed in a chip, there comes a point where the decrease in yield (percentage of good chips on a wafer) begins to outweigh the benefits of the chip’s increasing complexity. In short, a minimum transistor cost exists for each particular node of processing technology.

And here’s the crunch: that minimum cost per transistor has been rising since 28nm chips hit the market several years ago, says Henry Samueli, co-founder and chairman of Broadcom, a fabless semiconductor firm based in Irvine, California. That is partly a result of decreasing yields, but also because of the escalating cost of the photo-lithography equipment needed to fabricate ever-smaller integrated circuits. “The cost-effectiveness seems to have hit a sweet spot at about 28nm,” says Dr Samueli.

We passed that sweet spot some time ago. So what’s next? According to the article, something called Planar Opto-Electronic Technology (POET):

As it is, a technology known at POET, developed over the past 20 years by a team at the University of Connecticut, promises to power the next wave of innovation in integrated circuits—by using gallium arsenide to combine optics and electronics in a single chip.